`timescale 1ns/1ns

module clock_tb;
	reg clk;
	reg reset;
	reg ena;

	wire pm;
	wire [7:0] hh;
	wire [7:0] mm;
	wire [7:0] ss;

	clock uut (.clk(clk), .reset(reset), .ena(ena), .pm(pm), .hh(hh), .mm(mm), .ss(ss));

	initial begin
		clk = 1'b0;
		reset = 1'b0;
		ena = 1'b1;

		#2 reset = 1'b1;
		#2 reset = 1'b0;

		#172800;	// 2 day
	end

	always #1 clk = ~clk;

endmodule
